Although applicable to other similar semiconductor power components, the present invention and the problems on which it is based are described here with respect to a vertical IGBT (insulated gate bipolar transistor).
In general, IGBTs are used as power circuit-breakers in a cutoff voltage range from a few hundred volts to a few thousand volts. In particular, the use of such IGBTs as an ignition transistor, i.e., as a switch on the primary side of an ignition coil, is of particular interest.
The structure of a vertical IGBT resembles that of a VDMOS transistor, except that a p+ emitter is arranged on its anode side instead of an n+ substrate as in the VDMOS transistor. German Published Patent Application No. 31 10 230 discusses a vertical MOSFET component having the basic structure of a vertical IGBT. In principle, two types of vertical IGBT or V-IGBT are differentiated, namely the punch-through IGBT (PT) and the non-punch-through IGBT (NPT), as discussed by Laska et al., Solid-State Electronics, volume 35, no. 5, pages 681-685, for example.
The basic properties of these two types of IGBTs are described below with reference to FIGS. 2 and 3.
FIG. 2 shows a schematic cross-sectional diagram of an NPT-IGBT whose active region 10 includes cellular or strip-shaped MOS control heads 13, 14, 15, 16, 17. In particular, this shows a p-type body region 13, an n+ source 14, a p+ contact diffusion 15 for connecting p-type body region 13 to a cathode terminal 19, which is connected at the same time to n+ source region 14 and is at ground; there is also a gate electrode 16 and a gate oxide 17. In addition, there is an n-drift region 12, a p-emitter 11 on the rear side and an anode terminal 18; “d” denotes the thickness of p+ emitter 11 and 101 is a space charge region formed at the pn junction between p-type body region 13 and n-drift region 12.
The NPT-IGBT according to FIG. 2 may be produced on a low-doped n− substrate having a long charge carrier lifetime. After penetration of the diffusion profiles on the front side VS of the wafer to create MOS control heads 13, 14, 15, 16, 17, p+ emitter 11 is produced in a very shallow form with only a few μm depth of penetration (d≈few μm) and poor emitter efficiency on the rear side RS of the wafer. This transparent emitter region 11 has the function of ensuring a rapid shutdown of the current in dynamic operation of this component, with the goal of minimizing shutdown losses. To obtain satisfactory transmission properties despite such a poor emitter region 11, the carrier lifetime in the n− drift region 12 must be as high as possible. Furthermore, the thickness of n− drift region 12 is to be as small as possible, taking into account the desired blocking ability of the component. As a result of this, very thin wafers must be processed, especially in the range of blocking abilities of around 1 kV. This is a highly complex procedure and has become possible only in recent years (see, for example, T. Laska et al., Conf. Proc. ISPSD '97, pages 361-364).
FIG. 3 shows a schematic cross-sectional diagram of a PT-IGBT whose active region 20 includes cellular or strip-shaped MOS control heads 23, 24, 25, 26, 27. In particular, this shows a p-type body region 23, an n+ source region 24, a p+ contact diffusion 25 for connecting p-type body region 23 to a cathode terminal 29, which is connected at the same time to n+ source region 24; there is also a gate electrode 26 and a gate oxide 27. In addition, there is an n− drift region 22a and an n− buffer region 22b, a p+ emitter 21 on the rear side and an anode terminal 28; 201 denotes a space charge region formed at the pn junction between p-type body region 23 and n− drift region 22a. 
The PT-IGBT according to FIG. 3 may be produced on a thick p+-doped substrate, which at the same time forms rear-side emitter region 21, with epitactically applied n-buffer region 22b and epitactically applied n− drift region 22a. Since the thickness of n− drift region 22a is selected to be lower than required by the width of space charge region 201 in the drift region at the desired blocking ability to achieve the lowest possible on-state voltage drop, n-buffer region 22b has the function of preventing the space charge region from extending through to p+ emitter 21. To be able to achieve a rapid shutdown of the current despite good emitter 21, the charge carrier lifetime is kept small by lifetime killing, e.g., by electron bombardment, and/or the doping in n-buffer region 22b is selected to be high accordingly. The on-state voltage becomes higher with an increase in the buffer dose, so a good compromise may be achieved between the on-state voltage and the shutdown performance when using a highly doped thin buffer region 22b. Such as buffer is feasible only to a limited extent in the production of crude wafers using such a double EPI/substrate wafer due to buffer outward diffusion.
Therefore, there have been studies of PT-IGBTs on SDB (silicon direct bonding) wafers such as that already published by C. Yun et al., Conf. Proc. ISPSD '98, pages 261-264. With these SDB wafers, a buffer implant is introduced into an n− wafer of FZ silicon, and then this wafer is bonded directly to a p+ wafer of CZ silicon and healed. The resulting SDB crude wafer having the layer sequence n−n+p+ is then ground to the standard thickness and forms the starting basis for the production of PT-IGBTs according to the standard methods of semiconductor technology. This procedure may provide that with such SDB wafers, it is possible to produce very thin buffer regions having a high doping.
In an article by K. D. Hobart et al., 1999 Proc. IEEE, pages 45-49, an NPT-IGBT on SDB wafer material is discussed. In this case, however, the component is first produced on a standard n− wafer of FZ silicon including metallization. The bonding process with the method discussed there is complex and is performed following thin grinding of the wafer in a low-temperature process (T<450° C.) so as not to damage the IGBT structure which has already been metallized. Either an identical IGBT wafer or a p+ wafer is used as the bonding partner.
A brief explanation of the functioning of the IGBT types described here is given below.
For the on-state case with both types of IGBTs, gate electrode 16 or 26 is brought to a potential above the threshold voltage of MOS control heads 13, 14, 15, 16, 17 or 23, 24, 25, 26, 27, respectively, with respect to cathode terminal 19 or 29. Then an inversion channel is produced on the semiconductor surface beneath gate terminal 16 or 26 in the area of p-type body region 13 or 23. The semiconductor surface in the region of n− drift region 12 or 22a is then in the condition of accumulation. When there is a positive voltage at anode terminal 18 or 28 with respect to the cathode, electrons are injected into body regions 13 or 23 via n+ source regions 14 or 24, the MOS channels thus influenced, and the accumulation layer is injected into n− drift region 12 or 22a. 
Then anode-side emitter region 11 or 21 injects holes through which n− drift region 12 or 22a is flooded with charge carriers so that its conductivity is increased. It is in the high injection phase at on-state current densities. Therefore, an IGBT having a blocking ability above approx. 150-200 V is capable of carrying higher current densities having a lower voltage drop between the anode and cathode than a MOS transistor having the same breakdown voltage. In the on-state case, the current flows from the anode to the cathode. It is carried by electrons which are injected into n− drift region 12 or 22a and flow out via anode-side emitter 11 or 21 to the anode and by holes which are injected by the anode-side emitter into n− drift region 12 or 22a and flow toward the cathode via p-type regions 13, 15 or 23, 25.
In the blocking case, gate electrode 16 or 26 is brought to a voltage below the threshold voltage with respect to cathode terminal 19 or 29. If anode terminal 18 or 28 is then brought to a positive potential, then space charge region 101 or 201 arranged between p-type body region 13 or 23 and n− drift region 12 or 22a expands almost exclusively into n− drift region 12 or 22a. 
In the case of NPT-IGBT, the thickness of n− drift region 12 is selected to be larger than the width of space charge region 101 at a given maximum blocking ability of the component.
With the PT-IGBT, the thickness of n− drift region 22a is selected to be smaller than the width of the space charge region at a given maximum blocking ability of the component. To prevent space charge region 201 from running over onto p+ emitter region 21, n-doped buffer region 22b is introduced with the goal of preventing said punch-through.
FIG. 4 shows a circuit topology of another system in which a vertical IGBT 30′ is used as an ignition transistor in the primary circuit of an ignition coil for an internal combustion engine. For this application as an ignition transistor having the required blocking capacities of approx. 400-600 V, so far only PT-IGBTs on double EPI/substrate crude wafers have been used, thereby avoiding the problems of thin wafers with NPT-IGBTs as described above.
According to FIG. 4, vertical IGBT 30′ is connected to battery voltage 33 across an ignition coil 31. A spark plug 32 is provided on the secondary side of ignition coil 31. A diode 37 which is connected to control terminal 38 provides ESD protection, and resistors 35, 36 (e.g., where R36=1 kΩ and R35=10-25 kΩ) define the input resistance of the configuration as well as form the load of a clamping diode chain 34. Elements 30, 34, 35, 36, 37 may be monolithically integrated, diodes 37, 34 normally being made of polysilicon.
The circuit configuration according to FIG. 4 is operable directly by a suitable control unit via control terminal 38. To do so, a positive voltage of 5 V, for example, is applied to control terminal 38, whereupon a current increase is initiated through ignition coil 31. At a certain point in time, the voltage at control terminal 38 is reduced in increments to approx. 0 V, whereupon the voltage at node 39 increases steeply. This voltage increase is stepped up on the secondary side of ignition coil 31 and results in an ignition spark at spark plug 32.
Clamping diode chain 34 has the function of limiting the voltage rise at anode 39 to what is called the terminal voltage of approx. 400 V to protect IGBT 30′ and also to protect the other circuit components. This is important in particular in the pulse case which occurs, for example, when no ignition spark is generated, e.g., due to an ignition cable having fallen off. Then IGBT 30′ has to absorb the energy otherwise converted in the spark. Without such a voltage limitation, the anode voltage at node 39 would increase to the point of breakdown of IGBT 30′ and would destroy it. This is prevented by clamping diode chain 34 by the fact that on reaching a preselected terminal voltage, the gate of IGBT 30′ is triggered just strongly enough to prevent the voltage from exceeding the terminal voltage at node 39. Nevertheless, this operating case makes high demands on the pulse strength of IGBT 30′ due to the high energy converted, and it is not always possible to ensure these demands will be met to an adequate extent. The negative consequence would be destruction of IGBT 30′.
J. Yedinak et al., Conf. Proc. ISPSD, 1998, pages 399-402 have shown that a failure consequently occurs, as described in conjunction with FIG. 5.
FIG. 5 shows a schematic cross-sectional diagram of a PT-IGBT whose active region 40 includes cellular or strip-shaped MOS control heads 43, 44, 45, 46, 47. In particular, this shows a p-type body region 43, an n+ source region 44, a p+ contact diffusion 45 for connecting p-type body region 43 to a cathode terminal 49, which is connected at the same time to n+ source region 44; this also shows a gate electrode 46 and a gate oxide 47. In addition, there is an n− drift region 42a and an n-buffer region 42b, a rear-side p+emitter 41 and an anode terminal 48; 401 denotes a space charge region formed at the pn junction between p-type body region 43 and n− drift region 42a. 
In the pulse case, space charge region 401 covers entire n− drift region 42a. Electrons 402 are injected via the MOS channel that has developed in p-type body region 43 into n− drift region 42a, triggering p+ emitter 41 via a triggering of the gate controlled by said clamping diodes. Gain factor β of the pnp transistor formed by regions 41, 42a, 42b, 43 is higher at a high voltage than in the on state (see Takei et al., Conf. Proc. ISPSD, 1999, Appendix Paper 7.1), which is why a low triggering voltage at gate terminal 46 is sufficient to carry the load current and thus to limit the anode voltage to the terminal voltage. Due to the power loss which thus occurs, the component becomes very hot at the cathode in particular, whereupon an electron leakage current occurs. Electrons 403 run in the direction of the anode and control bias p+ emitter region 41 there. They thus act like an additional triggering of the IGBT. To keep the voltage at the level of the terminal voltage, triggering of gate terminal 46 is reduced via the terminal diode chain accordingly. Under certain operating conditions, the triggering due to the thermally induced electron leakage current is so strong that the IGBT is able to carry the load current without any gate control. Its controllability is lost. The temperature increases further and the leakage current also increases further, ultimately resulting in positive thermal feedback and destruction of the IGBT.